man page below, for now, see repo for [[https://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git/tree/gnucap-mg-vams.1?h=develop|current version]]. Relevant [[gnucap:projects:nlnet:verilogams|project page]].
Modelgen-verilog implementation notes are [[gnucap:manual:tech:modelgen|here]].

<code>
GNUCAP-MG-VAMS(1)             Gnucap Modelgen            GNUCAP-MG-VAMS(1)

NAME
       gnucap-mg-vams - GNU Circuit Analysis Package .vams translator

SYNOPSIS
       gnucap-mg-vams { [OPTIONS] [ACTIONS] }

DESCRIPTION
       Gnucap-Modelgen  is  a translator tool in the Gnucap suite. It will
       transform Verilog-AMS models into C++ code implementing Gnucap com‐
       ponent plugins.

       Basic usage (with bash, on a posix system)  may  look  as  follows.
       For more examples, see the examples directory.

       $  gnucap-mg-vams  -I  /path/to/include  --cc  mymodel.vams -o  my‐
       model.cc
       $ g++ `gnucap-conf --cppflags`  -fPIC  -shared  mymodel.cc  -o  my‐
       model.so
       $ gnucap -a ./mymodel.so -a mgsim
       gnucap> ...

       The mgsim directory contains the plugins used in modelgen models.

OPTIONS
       -I path
              Set preprocessor include path

       -D "name value"
              Set preprocessor constant

       -o "filename"
              Send output to filename (default: stdout).

       --flag | --noflag
              Various  flags,  under  construction, see mg_options.{h,cc}.
              Also available through `pragma during preprocessing.

ACTIONS
       --pp   dump preprocessor output

       --dump dump contents as parsed

       --cc   generate c++ file

COMPILER FLAGS
       These may be passed  to  the  compiler  supplementing  `gnucap-conf
       --cppflags`.

       -O0, -O2
              Turn on, off optimisation respectively. For details, consult
              your compiler manual.

       -g     Include  debugging  symbols.  For details, consult your com‐
              piler manual.

       -DNDEBUG
              Drop debugging code, essentially run time  assertions.  This
              will speed up execution significantly.

       -DTRACE_UNTESTED
              Discover  test  status.  Untested  code notification will be
              printed to standard error output.

       -DTRACE_ITESTED
              Similar, but notify about interactively tested code.

EXAMPLES
       Basic Verilog-AMS models are included with this  package,  covering
       some of the primitives listed in Table E.1 of the LRM 2.4.0.

       For  general  usage,  see examples directory shipped with modelgen-
       verilog source code.

BUGS
       This is under construction. Expect bugs, see BUGS.

AUTHOR
       Gnucap-mg-vams is being written by Felix Salfelder and Albert Davis
       with financial support from NLnet  Next  Generation  Internet  pro‐
       gramme.

       This   manual   page   was   written   by   Felix   Salfelder  <fe‐
       lix@salfelder.org>.  For the full documentation, visit  http://gnu‐
       cap.org.

Gnucap Project                   May 2023                GNUCAP-MG-VAMS(1)
</code>