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gnucap:manual:tech:spice2verilog [2025/11/24 02:09] felixs binning |
gnucap:manual:tech:spice2verilog [2025/11/24 02:18] (current) felixs binning: reusability remark |
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| mymos #(.w(2.5)) M2(.d(d),.gate(g),.s(s),.b(b)); | mymos #(.w(2.5)) M2(.d(d),.gate(g),.s(s),.b(b)); | ||
| - | as expected, optionally with port names inferred from mymos_wrap. | + | as expected, optionally with port names inferred from mymos_wrap. Note that these paramsets are self contained and reusable specifically when moving on from Spice "model + instance" .subckt wrappers to behavioural models implemented as Verilog "module". |
| === Type nesting === | === Type nesting === | ||