In late '22, we have secured some [[https://nlnet.nl/project/Gnucap-VerilogAMS/|funding]] from the NLnet Foundation alowing us to work on Verilog-AMS support. Within the next months, we will work on two tasks. One task is a compiler for behavioural models, the other is Verilog support on the simulator level.

Each task has 8 milestones. Here we will give details and keep track of our progress.

=== Task 1. modelgen-verilog: Provide a replacement for ADMS ===

== a) Implement Verilog-AMS style branches and contributions ==
== b) Generate partial derivatives of expressions, needed by Newton's method ==
== c) Snapshot release supporting minimalistic devices with test suite. ==
== d) Support for loops, conditionals and built-ins as plugins. ==
== e) Add specific commonly used language features, ddt, idt. ==
== f) Include test cases from the LRM and the Designers Guide. ==
== g) Write user documentation and technical notes. ==
== h) Set up examples involving common third party compact models. ==

=== Task 2. Verilog-AMS compliance on the simulator level ===

== a) Model overloading by name and parameter ranges according to standard. ==
Verilog defines "paramset" as a means to replace model cards known from spice, cf. LRM section 6.4.
The standard essentially allows multiple prototypes by the same name with mutually different interfaces [[gnucap:manual:languages:verilog#paramset|usage]].
This requires changes to the way device instances are read in and elaborated [[paramset_implementation|TODO_IMPL]].
== b) Implement preprocessor, support backtick, macros, conditionals. ==
== c) Add support for "attribute instance". ==
== d) Provide logic gates as plug-ins, accessible from Verilog netlists. ==
== e) Refactor internals; make dc sweep work with parameters. ==
Historically the dc sweep command only sweeps elements. Currently, in Gnucap sweeping parameters is more tedious than in other simulators. We will adjust and redefine the data path for parameter values [[precalc_last|TODO_IMPL]], and extend the dc command plugin to make use of it.
== f) Integrate "model card" hierarchy into Verilog language semantics. ==

To be able to use models implemented for Spice in a Verilog environment, we need to be able to reference these models from paramset statements.
Spice has both component letters and model identifiers, whereas Verilog only uses type names [[gnucap::paramset_spice|etc.]]. Spice hardwires the segmentation into
shared and individual storage, while Verilog leaves it to the user. We may have to find a way to avoid performance regressions.
== g) Revisit build system: Improve model compilation and loading ==
Currently, Gnucap loads precompiled binary plugins. We will automate the compilation process for a better user experience, especially because Verilog-AMS behavioural code must be compiled prior to loading.
== h) Release all of the above ==