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--- gnucap:user:netlist_import_and_export [2024/07/09 19:01]
aldavis [Adding physical position]
+++ gnucap:user:netlist_import_and_export [2024/07/30 12:52] (current)
aldavis [Mapping to the application]
@@ Line 165: / Line 165: @@
     opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .pn(b3));
-    net a (.1(a0), .2(a1));
+    net a (a0, a1);
-    net b (.1(b1), .2(b2), .3(b3));
+    net b (b1, b2, b3);
-    net c (.1(c0), .2(c2), .3(c3));
+    net c (c0, c2, c3);
   endmodule
-We have replaced the nodes with nets, which are now first class objects.
+We have replaced the nodes with nets, which are now first class objects.   This will give us a way to represent the interconnect in a schematic drawing or a layout.  It also provides essential data to support analysis and simulation of the interconnect.
 Looking at net "b" as an example, it has 3 connections : r1 pin n, p2 pin p, and u1 pin pn.
@@ Line 198: / Line 199: @@
 | PC     | Printed Circuit Layout |
 | L      | IC Layout              |
 We add a third dimension "z", and a third flip "zflip".  We shorten xposition to x, yposition to y, and add a number to have multiple positions.  The "z" may indicate a layer name instead of a dimension, depending on the application.
 ==== Adding physical position ====
-Now we use the attributes to specify the location.  All positions indicate a place where a connection is made, or could be made.  Then the positions of things that connect there can be determined.  I am thinking schematic for now, but the same concept applies to layout.  It is not necessary to place all of the nodes because others can be implied, but you could as a check or to imply flip and rotate.  If they are inconsistent, rubberbanding would preserve connectivity.  Usually, you can place one node per component, and let the nets float, except that you could add extra nodes to nets so you can place junctions.
+Now we use the attributes to specify the location.  We need to locate the various objects.  In most cases, we need to specify some point of every object that will identify its location.  Some programs use some notion of a "center", which is ambiguous.  We will use the electrical connection points, often called "pins", as the location points for things that have an electrical connection.  For objects that do not have electrical connections, reference points can be used.
+We will number the pins, by position, 1, 2, ...  Then we use x1,y1, and so on to locate them.  Usually one of them is adequate to locate an object.  The others can "float", allowing the actual location to be determined by the surroundings.  It is permissible to overspecify locations, provided they are self-consistent, and consistent with connections.
+Pin numbering starts at 1 (not 0) to be consistent with most IC and connector pin numbering.
+In addition to the positions, hflip, vflip, and angle are supported.  If there is both a flip and an angle, flip will be done first, then angle.
+Another attribute named for the specific tool (example: S0_geda) can be used to stash tool specific data that doesn't fit otherwise.  This is intended to assist with a translation from this format back to the tool format.  Normally, this would be a string containing a composite of the info (S0_geda="5 10 0 0 0 0 1")  If more than one string in a scope is needed, suffixes can be used. (S0_geda_color="blue" S0_geda_symbol="resistor-1.sym")  These are stored and passed on without any interpretation.
   module amp (.a(a0), .c(c0));
     (* S0_x1=-5m, S0_y1=0m *)  input a0;
     (* S0_x1=30m, S0_y1=-3m *) output c0;
+                               ground g0;
+                               ground g1;
     (* S0_x1=0m,  S0_y1=0m *)  resistor #(.r(1k))      r1 (.p(a1), .n(b1));
     (* S0_x1=24m, S0_y1=7m *)  resistor #(.r(1k))      r2 (.p(b2), .n(c2));
-    (* S0_x1=25m, S0_y1=-3m *) opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));
+    (* S0_x1=25m, S0_y1=-3m *) opamp741 #(.gain(100k)) u1 (.p(c3), .n(g1), .ps(g0), .ns(b3));
-    net a (.1(a0), .2(a1));
+    net a (a0, a1);
-    net b (.1(b1), .2(b2), .3(b3));
+    net b (b1, b2, b3);
-    net c (.1(c0), .2(c2), .3(c3));
+    net c (c0, c2, c3);
   endmodule
   * This is a schematic, using a 1 mm grid.
-  * The location of node "a1" is being used as a reference here, (0,0).  This is the "p" pin of "r1".
+  * The lines "input" and "output" are pins, explicitly located.
-  * The location of node "b2" is (24,7).  This is the "p" pin of "r2".
+  * The lines "resistor" and "opamp741" are components, explicitly located by pin 1 of each, all called "p" here, by coincidence.
-  * The location of node "c3" is (25,-3).  This is the "p" pin of "u1".
+  * The lines "ground" are the ground symbol.  The first is node "g0", which is the "ps" pin ("+" input, pin 2) of "u1", so it is implicitly located there.  The other is node "g1", which is the "n" pin (pin 1) of "u1", so this one is also implicitly located.  An explicit location could have been specified, but is not necessary because it can be determined by the symbol for "u1".
   * The location of other nodes will follow based on the symbol or footprint geometry.
   * It is ok to leave some, or even most, unspecified, so they will be located by context.
   * It is ok to locate a node more than once, provided the locations are the same.
   * If locations of the same node are not the same, the tool shall issue a warning, and make a correction to assure connectivity is correct.
-  * Locating one node of a footprint or symbol determines the location of the symbol or footprint.
+  * Locating one pin of a footprint or symbol determines the location of the symbol or footprint.
   * In the above example, the I/O pins and components have been explicitly located.
   * The nets have been implicitly located.
@@ Line 232: / Line 243: @@
 The choice of which nodes to locate could have been different.  The following example produces exactly the same result.
   module amp (.a(a0), .c(c0));
     input a0;
     output c0;
+    ground g0;
+    ground g1;
     resistor #(.r(1k))      r1 (.p(a1), .n(b1));
     resistor #(.r(1k))      r2 (.p(b2), .n(c2));
-    opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));
+    opamp741 #(.gain(100k)) u1 (.p(c3), .n(g1), .ps(g0), .ns(b3));
-    (* S0_x1=-5m, S0_y1=0m,  S0_x2=0m,  S0_y2=0m *)  net a (.1(a0), .2(a1));
+    (* S0_x1=-5m, S0_y1=0m,  S0_x1=0m,  S0_y1=0m *)  net a (a0, a1);
-    (* S0_x2=24m, S0_y2=7m *)                        net b (.1(b1), .2(b2), .3(b3));
+    (* S0_x2=24m, S0_y2=7m *)                        net b (b1, b2, b3);
-    (* S0_x1=30m, S0_y1=-3m, S0_x1=25m, S0_y1=-3m *) net c (.1(c0), .2(c2), .3(c3));
+    (* S0_x1=30m, S0_y1=-3m, S0_x2=25m, S0_y2=-3m *) net c (c0, c2, c3);
   endmodule
+The following example is over determined, but legal, and produces the same result.
+  module amp (.a(a0), .c(c0));
+    (* S0_x1=-5m, S0_y1=0m *)  input a0;
+    (* S0_x1=30m, S0_y1=-3m *) output c0;
+                               ground g0;
+                               ground g1;
+    (* S0_x1=0m,  S0_y1=0m *)  resistor #(.r(1k))      r1 (.p(a1), .n(b1));
+    (* S0_x1=24m, S0_y1=7m *)  resistor #(.r(1k))      r2 (.p(b2), .n(c2));
+    (* S0_x1=25m, S0_y1=-3m *) opamp741 #(.gain(100k)) u1 (.p(c3), .n(g1), .ps(g0), .ns(b3));
+    (* S0_x1=-5m, S0_y1=0m,  S0_x2=0m,  S0_y2=0m *)  net a (a0, a1);
+    (* S0_x2=24m, S0_y2=7m *)                        net b (b1, b2, b3);
+    (* S0_x1=30m, S0_y1=-3m, S0_x3=25m, S0_y3=-3m *) net c (c0, c2, c3);
+  endmodule
 ==== Multiple applications, both layout and schematic ====
-Portions that apply in only certain contexts can be selectively included with 'ifdef:
+Files can be combined.
   module amp (.a(a0), .c(c0));
-    resistor #(.r(1k)) r1 (.p(a1), .n(b1));
+    input a0;
-    resistor #(.r(1k)) r2 (.p(b2), .n(c2));
+    output c0;
-    opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .pn(b3));
-    net a (.1(a0), .2(a1));
+    resistor #(.r(1k))      r1 (.p(a1), .n(b1));
-    net b (.1(b1), .2(b2), .3(b3));
+    resistor #(.r(1k))      r2 (.p(b2), .n(c2));
-    net c (.1(c0), .2(c2), .3(c3));
+    opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));
-  `ifdef SCHEMATIC
+    (* S0_x0=-5m, S0_y0=0m,  S0_x1=0m,  S0_y1=0m,  PC0_x0=-5m, PC0_y0=0m,  PC0_x1=0m,  PC0_y1=0m *)  net a (a0, a1);
-    place #(.$xposition(24m), .$yposition(7m))  place_b2 (b2);
+    (* S0_x1=24m, S0_y1=7m *)                   (* PC0_x1=24m, PC0_y1=7m *)                          net b (b1, b2, b3);
-    place #(.$xposition(0m),  .$yposition(0m))  place_a1 (a1);
+    (* S0_x0=30m, S0_y0=-3m, S0_x2=25m, S0_y2=-3m, PC0_x0=30m, PC0_y0=-3m, PC0_x2=25m, PC0_y2=-3m *) net c (c0, c2, c3);
-    place #(.$xposition(25m), .$yposition(-3m)) place_c3 (c3);
-  `endif
-  `ifdef LAYOUT
-    place #(.$xposition(1000u), .$yposition(0u)) place_b2 (b2);
-    place #(.$xposition(0m),    .$yposition(0u)) place_a1 (a1);
-    place #(.$xposition(2000u), .$yposition(0u)) place_c3 (c3);
-  `endif
   endmodule
-==== Mapping to the application ====
+Portions that apply in only certain contexts can be selectively included with '''ifdef''.  This may be useful when the component list needs to be different for the different applications, such as when the nets have different forms for a different route or parameters.  Macros like ''%%__S0__%%'' and ''%%__S0__geda__%%'' are automatically predefined if appropriate.  These macros should not be defined in the file, except temporarily for debugging.
-Paramset and module can be used, with ifdef, to add info that may be needed for particular applications.
+  module amp (.a(a0), .c(c0));
+    input a0;
-  `ifdef GSCHEM
+    output c0;
-    paramset opamp741 symbol
-      .file(opamp4.sym);
+    resistor #(.r(1k))      r1 (.p(a1), .n(b1));
-    paramset resistor symbol
+    resistor #(.r(1k))      r2 (.p(b2), .n(c2));
-      .file(resistor2.sym);
+    opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));
-  `endif
-  `ifdef SIMULATION
+  `ifdef __S0__
-    module opamp741 ( .....
+    (* S0_x0=-5m, S0_y0=0m,  S0_x1=0m,  S0_y1=0m *)  net a (a0, a1);
-      .....
+    (* S0_x1=24m, S0_y1=7m *)                        net b (b1, b2, b3);
-    endmodule
+    (* S0_x0=30m, S0_y0=-3m, S0_x2=25m, S0_y2=-3m *) net c (c0, c2, c3);
+  `elsif __PC0__
+    (* PC0_x0=-5m, PC0_y0=0m,  PC0_x1=0m,  PC0_y1=0m *)  net a (a0, a1);
+    (* PC0_x1=24m, PC0_y1=7m *)                          net b (b1, b2, b3);
+    (* PC0_x0=30m, PC0_y0=-3m, PC0_x2=25m, PC0_y2=-3m *) net c (c0, c2, c3);
+  `else
+    net a (a0, a1);
+    net b (b1, b2, b3);
+    net c (c0, c2, c3);
   `endif
+  endmodule
-==== Complex nets can be encapsulated ====
+==== Mapping to the application ====
-  module net23842 (1,2,3);
+It is intended that the verilog type (resistor, opamp741, net in this example) and the parameter lists (''#(...)'') could be used directly by a simulator or other tool, but also allowing substitution using whatever mechanism the tool provides, which could be __module__ or __paramset__ in Verilog.
-    net n23482 (1,2);
-    net n84333 (2,3);
-    `ifdef SCHEMATIC
-      place ...
-      place ...
-      place ...
-    `endif
-  endmodule
-  module net9393 (1,2);
+For symbols (in schematics) or footprints (layout), ideally this mapping would be resolved automatically globally.  Alternatively, in could be resolved locally using an attribute.
-    net #(.color(blue), .thickness(thin)) n38423 (1,2);
-  endmodule
-==== Hierarchy ====
+  (* S0_geda_symbol="resistor2.sym" *) resistor #(10k) r4 (a,b);
-The system supports hierarchy.
-  module twoamps (in, out);
-    amp a1 (in, mid1);
-    amp a2 (mid2, out);
-    net mid (mid1, mid2);
-  'ifdef SCHEMATIC
-    place #(.$xposition(0),   .$yposition(0)) place_in  (in);
-    place #(.$xposition(30m), .$yposition(0)) place_mid (mid2);
-  'endif
-  endmodule