Gnucap behavioral modeling is in a state of transition, so this is subject to change in a future release. All simple components can have a behavioral description, with syntax designed as an extension of the Spice time dependent sources. They are not necessarily physically realizeable. Some only work on particular types of analysis, or over a small range of values. Some can be used together, some cannot. All simple components are considered to have simple transformations. A function returns one parameter as a function of one other, as an extension of their linear behavior.
Such simple components are Capacitor, Inductor, Resistor, Admittance, as well as controlled sources
VCVS, VCCS, CCVS, CCCS etc. These may be controlled with functions depending on time, nonlinear transfer functions or tables. The syntax for this is inspired by Spice, but more regular. For example V12 (1 0) AC 1 DC 3. This declares a voltage source with a value of 1 for AC analysis, 3 for DC. OP, Transient, and
Fourier inherit the DC value.
Spice has grown into all kinds of mutually incompatible directions, adding very flexible modelling capabilities. Some offer B devices interpreting a variety of expressions, some have primitives for discrete modelling. In the past decades, the Verilog-AMS standard has been introduced. It simplifies the implementation of quite generic models, in a portable manner, without the need for a real programming language. Here, the basic concept behind analog modelling is controlling sources by means of imperative-style code that takes probe values as input. Chapter 9 of the Verilog-AMS LRM list the functions, filters and tasks that we aim to support in modelgen-verilog. These are implemented as plugins, covering most of the functionality of the original approach, and share the implementation and algorithms where applicable. See here for an overview and progress.
To simplify the transition from Spice, Verilog-AMS offers some degree of compatibility, see Annex E in the LRM. This also includes a standardised set of primitives that act as drop in replacements for component instantiations in a Spice netlist. This set of primitives is under construction in modelgen-verilog (see here), and precompiled plugins are being installed with it.)